Memory device

Details Memory device Memory device

G - Physics

06

F

354/231

G06F 13/00 (2006.01) G06F 11/10 (2006.01) G06F 11/16 (2006.01)

Patent

CA 2022249

ABSTRACT OF THE DISCLOSURE A memory for storing data in a computer system. Integrity of data transferred to or from a memory array is monitored by transferring two sets of EDC or ECC data corresponding to a longword of data between the memory array and two separate memory controllers. The probability of an undetected error is very low because the two sets of EDC or ECC data are compared to ensure that they match. The number of lines and pins used is minimized by multiplexing the EDC or ECC data with address signals and cycle type signals. The address and cycle type signals are placed on the time division multiplexed bidirectional lines at the beginning of a memory transfer cycle, and the EDC or ECC data is placed on these time division multiplexed lines at times when a longword of data is being transferred on a set of bidirectional data lines.

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