Method and apparatus for reducing latency in a memory system

Details Method and apparatus for reducing latency in a memory system Method and apparatus for reducing latency in a memory system

G - Physics

06

F

G06F 13/38 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2327134

A memory controller controls a buffer which stores the most recently used addresses and associated data, but the data stored in the buffer is only a portion of a row of data (termed row head data) stored in main memory. In a memory access initiated by the CPU, both the buffer and main memory are accessed simultaneously. If the buffer contains the address requested, the buffer immediately begins to provide the associated row head data in a burst to the cache memory. Meanwhile, the same row address is activated in the main memory bank corresponding to the requested address found in the buffer. After the buffer provides the row head data, the remainder of the burst of requested data is provided by the main memory to the CPU.

Un contrôleur de mémoire commande une mémoire tampon qui stocke les adresses et les données connexes les plus récemment utilisées. Toutefois, les données stockées dans la mémoire tampon ne constituent qu'une partie d'une ligne de données (les données d'en-tête de ligne) stockée dans la mémoire principale. Lorsque l'UC interroge la mémoire, la mémoire tampon et la mémoire principale sont consultées simultanément. Si la mémoire tampon contient l'adresse demandée, elle commence immédiatement à fournir les données d'en-tête de ligne correspondantes en rafale à la mémoire cache. Entre-temps, la même adresse de ligne est activée dans le bloc mémoire principal correspondant à l'adresse demandée, stockée dans la mémoire tampon. Une fois que la mémoire tampon a fourni les données d'en-tête de ligne, la mémoire principale complète la rafale de données demandées en les envoyant à l'UC.

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