Method and apparatus for reducing data delay within a...

Details Method and apparatus for reducing data delay within a... Method and apparatus for reducing data delay within a...

G - Physics

06

F

G06F 15/163 (2006.01) H04J 3/04 (2006.01) H04J 3/16 (2006.01) H04N 7/58 (2006.01)

Patent

CA 2186918

A multi-channel integrated circuit, which includes N processing channels and a functional circuit which is time-shared between each of the N channels for processing data in accordance with a first clock strobe. Also included is a time-division multiplexed bus for providing synchronized data to and receiving synchronized data from said circuit in accordance with a second clock strobe. The data are thereby processed within said shared circuit in synchronization with said first and second clock strobes.

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