Circuit arrangement and method for forward error correction

Details Circuit arrangement and method for forward error correction Circuit arrangement and method for forward error correction

H - Electricity

04

L

H04L 1/00 (2006.01) H03M 13/05 (2006.01) H04J 3/14 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 2304249

In order to allow forward error correction in data transport systems, the data of a transport framework are gathered in error correction blocks and parity check bits are specially provided for that purpose. Such parity check bits are then integrated into a free area in the section overhead of the same error correction block.

Pour permettre la correction d'erreur sans circuit de retour dans les systèmes de transport de données, les données d'un cadre de transport sont regroupées en blocs de correction d'erreur et des éléments binaires de parité prévus à cet effet: Ces éléments binaires de parité sont ensuite intégrés à un secteur libre de surdébit de section du même bloc de correction d'erreur.

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