Method and system of addressing

Details Method and system of addressing Method and system of addressing

G - Physics

06

F

G06F 9/38 (2006.01) G06F 9/32 (2006.01) G06F 9/355 (2006.01)

Patent

CA 2159888

An improved method of addressing within a pipelined processor having an address bit width of m + n bits is disclosed, which includes storing m high order bits corresponding to a first range of addresses, which encompasses a selected plurality of data executing within the pipelined processor. The n low order bits of addresses associated with each of the selected plurality of data are also stored. After determining the address of a subsequent datum to be executed within the processor, the subsequent datum is fetched. In response to fetching a subsequent datum having an address outside of the first range of addresses, a status register is set to a first of two states to indicate that an update to the first address register is required. In response to the status register being set to the second of the two states, the subsequent datum is dispatched for execution within the pipelined processor. The n low order bits of the subsequent datum are then stored, such that memory required to store addresses of instructions executing within the pipelined processor is thereby decreased.

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