Chip assay having improved efficiency

G - Physics – 01 – N

Patent

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Details

G01N 27/416 (2006.01) C40B 30/04 (2006.01) C40B 60/00 (2006.01) C40B 60/12 (2006.01) C40B 80/00 (2006.01) G01N 27/327 (2006.01) G01N 27/403 (2006.01) G01N 33/53 (2006.01) G01N 33/577 (2006.01) G01N 27/30 (2006.01)

Patent

CA 2690190

The chip includes electrodes on a substrate. The electrodes include a working electrode, a reference electrode, and a counter electrode. The reference electrode is constructed so as to not have an intrinsic potential. A self-assembly monolayer is positioned on the reference electrode. The self-assembly monolayer includes spacers and active probes. The active probes are configured to have a higher affinity for a capture probe than the spacers have for the capture probe.

La puce comprend des électrodes sur un substrat. Les électrodes comprennent une électrode de travail, une électrode de référence et une contre-électrode. L'électrode de référence est construite de façon à ne pas avoir un potentiel intrinsèque. Une monocouche à auto-assemblage est positionnée sur l'électrode de référence. La monocouche à auto-assemblage comprend des espaceurs et des sondes actives. Les sondes actives sont configurées pour avoir une affinité pour une sonde de capture supérieure à celle que les capteurs ont pour la sonde de capture.

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