Serial data transfer process, and synchronous serial bus...

Details Serial data transfer process, and synchronous serial bus... Serial data transfer process, and synchronous serial bus...

G - Physics

06

F

G06F 13/372 (2006.01) G06F 13/42 (2006.01)

Patent

CA 2261840

The synchronous serial bus (13) between a main processing unit (10) and a peripheral unit (12) includes a data line (BDA) and a clock line (BCL). Strobe pulses presented by the main processing unit (10) on the data line while it holds the clock line at a given logic level characterise transfer cycles on the bus (13). The main processing unit (10) can thus run write or read cycles in registers of an interface (16) of the peripheral unit (12). A direct transfer mode, wherein the strobe pulse is transmitted at the beginning of the cycle without specifying an address, is provided to enable the main processing unit (10) to have a fast access to certain locations previously specified. The data and clock lines (BDA,BCL) of the bus (13) may be shared with those of another synchronous bus (11).

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