G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 13/14 (2006.01) G06F 12/02 (2006.01) G06F 12/08 (2006.01)
Patent
CA 2264518
A cache-coherent, multiple-bus, multiprocessing system and method interconnects multiple system buses (1, 2) and an I/O bus (3) to a shared main memory (132) and efficiently maintain cache coherency while minimizing the impact to latency and total bandwidth within the system. The system provides coherency filters (200) which coordinate bus- to-bus communications in such a way as to maintain cache memory coherency with a small amount of cross-bus traffic. In addition, the system provides a multiported pool of memory cells which interconnect the multiple buses.
L'invention porte sur un système multiprocesseurs, à cohérence entre antémémoires et à bus multiples (1, 2), ainsi que sur la méthode correspondante, permettant de connecter de multiples bus système et un bus d'entrée-sortie (3) à une mémoire principale partagée (132) ainsi que de conserver efficacement une cohérence entre antémémoires tout en minimisant toute incidence sur la latence et la largeur de bande totale au sein du système. Ce système comporte des filtres de cohérence (200) qui coordonnent des communications entre bus de manière à conserver une cohérence entre antémémoires dans le cas d'un petit volume de trafic entre bus. Ce système comporte, de surcroît, un regroupement de cellules mémoire à accès multiples connectant les bus multiples.
Chang Stephen S.
Vogt Pete D.
White George P.
Corollary Inc.
Intel Corporation
Smart & Biggar
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