Insulated gate field-effect transistor read-only memory array

Details Insulated gate field-effect transistor read-only memory array Insulated gate field-effect transistor read-only memory array

G - Physics

11

C

354/241, 352/82.

G11C 11/40 (2006.01) G11C 16/04 (2006.01) H01L 29/792 (2006.01)

Patent

CA 1067208

ABSTRACT OF THE DISCLOSURE An array of read-only memory cells is formed from a plurality of insulated gate field-effect transistors. Information may be programmed into individual transistors within the array by application of selected potentials to the connecting lines of the array. An individual cell is programmed by causing some of the electrons flowing between the source and drain to acquire sufficient energy to be injected into and trapped in the insulating material separating the channel from the gate electrode. The trapped electrons cause a change in the current-voltage characteristics of the transistor, which may be detected during reading of the memory cell most easily by reversing the polarity of the source and the drain Embodiments of such an array are shown and may be utilized as a ROM, PROM or EPROM.

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