Pipelined sample and hold circuit with correlated double...

Details Pipelined sample and hold circuit with correlated double... Pipelined sample and hold circuit with correlated double...

G - Physics

01

D

G01D 3/032 (2006.01) G11C 27/02 (2006.01)

Patent

CA 2244683

A signal sampling circuit for performing correlated double sampling (CDS) of an input signal with a pipelined sample and hold architecture includes a time multiplexed integrating amplifier circuit in which the output circuit is a pipelined sample and hold circuit which provides time multiplexed input signal samples and the feedback integration capacitor is discharged between samples. At all times, one of the channels of the pipelined sample and hold circuit is providing one of the time multiplexed input signal samples while the other channel continues tracking the input signal. The feedback integration capacitor acts as a clamp to null out residual reset noise received as part of the input signal to be sampled. Hence, with the exception of that very brief period of time necessary for switching between the two pipelined sample and hold circuit channels, one of the two pipelined sample and hold circuit channels is always available for signal acquisition.

L'invention porte sur un échantillonneur/bloqueur permettant d'effectuer un double échantillonnage corrélé (CSD) sur un signal d'entrée comportant une architecture pipelinisée d'échantillonneur/bloqueur comprenant un circuit amplificateur intégrateur multiplexé dont le circuit de sortie est un circuit échantillonneur/bloqueur pipelinisé fournissant des échantillons du signal d'entrée à multiplexage temporel et dont le condensateur d'intégration rétroactive se décharge entre les échantillons. A tout moment l'un des canaux du circuit échantillonneur/bloqueur pipelinisé fournit l'un des échantillons du signal d'entrée à multiplexage temporel, tandis que l'autre canal continue à suivre le signal d'entrée. Le condensateur d'intégration de rétroaction sert de verrou annulant le bruit résiduel de remise à zéro reçu faisant partie du signal d'entrée à échantillonner. De ce fait, à l'exception de la très courte période nécessaire pour la commutation entre les deux canaux de l'échantillonneur/bloqueur pipelinisé, l'un de ces canaux reste toujours disponible pour l'acquisition de signaux.

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