Interrupt controller for multiprocessor systems

Details Interrupt controller for multiprocessor systems Interrupt controller for multiprocessor systems

G - Physics

06

F

354/230.82

G06F 13/24 (2006.01) G06F 13/00 (2006.01) G06F 13/26 (2006.01)

Patent

CA 2011388

In a multiprocessor system, a request from a processor for data transfer between an external mass storage unit and a main memory is granted and a report indicating an event is supplied from the external storage unit if there is one to report. An event decoder decodes the reported event and makes a first decision if it is a sync-related event resulting from the execution of an instruction and makes a second decision if it is a sync-unrelated event irrelevant to execution of instructions. One of the processors except for the granted processor is selected as a master processor to be interrupted when a sync-unrelated event occurs. An interrupt generator supplies an interrupt to the request-granted processor when the first decision is made by the decoder or supplies it to the selected master processor if the second decision is made. When an event such as overvoltages and high temperatures occur during data transfer, the processor requesting such transfer is prevented from being indiscriminately interrupted.

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