Field effect transistor, control method for controlling such...

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H01L 29/772 (2006.01) H01L 27/088 (2006.01) H01L 29/08 (2006.01) H03D 7/14 (2006.01)

Patent

CA 2270662

The field effect transistor includes a control terminal (G), a first main terminal (S) and a second main terminal (D1). The control terminal (G) is included to be coupled to gate voltage means which. are adapted to provide a control voltage (V g) which controls a flow of carriers (e) flowing from the first main terminal (S) to the second main terminal (D1). The field effect transistor further includes a third main terminal (D2) which is positioned and adapted in order to enable a high. input resistance control current means (CS), which is coupled to the third main terminal (D2), to deviate part (e') of the flow of carriers from the first main terminal (S) to the third main terminal (D2). The third main terminal is called the double drain (D2) of the field effect transistor.

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