System and method including distributed instruction buffers...

G - Physics – 06 – F

Patent

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G06F 9/38 (2006.01)

Patent

CA 2444543

A processor for processing a first instruction form and a second instruction form of an instruction set comprises execution units (301-305) connected to an instruction fetch unit (322) for the first instruction form and a sequencer (325) for the second instruction form. The processor comprises a decode unit (323) for decoding instructions of the first instruction form into control signals for the execution units (301-305), and buffers (306-310), proximate to the execution units (301-305), for storing predecoded instructions of the second instruction form.

La présente invention concerne un processeur destiné au traitement d'une première forme d'instructions et d'une seconde forme d'instructions d'un jeu d'instructions. Il comprend des unités d'exécution (301 305) connectées à une unité de lecture d'instructions (322) pour la première forme d'instructions, et un séquenceur (325) pour la seconde forme d'instructions. Le processeur comprend une unité de décodage (323) pour décoder en signaux de commande pour les unités d'exécution (301 305) les instructions de la première forme d'instructions, et, à proximité des unités d'exécution (301 305), des tampons (306 310) de stockage des instructions prédécodées de la seconde forme d'instructions.

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