Hdtv receiver

Details Hdtv receiver Hdtv receiver

H - Electricity

04

N

H04N 7/08 (2006.01) H04N 5/44 (2006.01) H04N 7/015 (2006.01) H04N 7/28 (2006.01) H04N 7/32 (2006.01) H04N 7/50 (2006.01) H04N 7/60 (2006.01)

Patent

CA 2054593

An HDTV receiver design includes a reconstruction section and an inner loop section. The reconstruction section comprises a receiving section for accepting the television receiver's antenna signals, for separating out the component signals from the received signals and for decoding the separated signals. The decoded signals are applied to a quantization decoder that is responsive to vector codebook and to applied quantized vector signals, and the output signals of the quantization decoder are applied to an inverse DCT circuit. The inner loop comprises an adderfor adding an estimate signal to the output of the DCT circuit, a frame buffer, a motion compensation circuit that is capable of translating large blocks as well as small blocks and a leak circuit that modulates the output of the motion compensator circuit in accordance with a received leak control signal. The input to the frame buffer is also applied to conventional amplification and display circuits to form the familiar output of a television receiver.

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