Tolerant in-system programming of field programmable gate...

G - Physics – 06 – F

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G06F 17/50 (2006.01)

Patent

CA 2666391

Fault tolerant programming of a programmable device (14) advantageously occurs via a host controller (20) that first queries the programmable device through a Boundary scan interface (18) to identify the device. Thereafter, host controller selects a program file in accordance with the device identity for subsequent downloading via the Boundary scan interface to program the device. Thereafter, the host controller verifies that successful programming has occurred.

La programmation à tolérance de pannes d'un dispositif programmable (14) se produit de manière avantageuse via un contrôleur hôte (20) qui demande en premier lieu au dispositif programmable, au moyen d'une interface de registre à décalage périphérique (18), d'identifier le dispositif. Par la suite, le contrôleur hôte sélectionne un fichier de programme en fonction de l'identité du dispositif pour le téléchargement subséquent via l'interface de registre à décalage périphérique pour programmer le dispositif. Par la suite, le contrôleur hôte vérifie qu'une programmation réussie a été obtenue.

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