Field effect transistor

Details Field effect transistor Field effect transistor

H - Electricity

01

L

H01L 29/812 (2006.01) H01L 29/10 (2006.01)

Patent

CA 2104745

ABSTRACT OF THE DISCLOSURE It is an object of the present invention to provide a dual-gate type MESFET having a high drain breakdown voltage and excellent high-frequency characteristics. A semiconductor substrate used in the present invention is obtained by sequentially forming a non-doped buffer layer 2, a thin first pulse-doped layer 3 having a high impurity concentration, and a cap layer 7 on an underlying semiconductor substrate 1 by epitaxial growth. The cap layer 7 has a thin second pulse-doped layer 5 having a high impurity concentration sandwiched between non-doped layers 4 and 6. The thickness and impurity concentration of the second pulse-doped layer 5 are set such that the second pulse-doped layer 5 is depleted by a surface depletion layer caused by the interface state of the cap layer surface, and the surface depletion layer does not extend to the first pulse-doped layer 3. A source electrode 13, a drain electrode 16, and first and second gate electrodes 14 and 15 are formed on the semiconductor substrate surface. High-impurity-concentration ion implantation regions 10, 11, and 12 are formed at a source electrode formation region, a drain electrode formation region, and a region between the first and second gate electrode formation regions to extend from the semiconductor substrate surface to the first pulse-doped layer 3. The second electrode 15 formed on the drain electrode 16 side is sufficiently separated from the high-impurity-concentration ion implantation region 12 below the drain electrode 16.

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