Method and apparatus for an interleaved non-blocking packet...

H - Electricity – 04 – L

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H04L 29/02 (2006.01) G06F 12/06 (2006.01) H04L 12/56 (2006.01)

Patent

CA 2383458

Memory interleaving is performed to increase bandwidth of a common memory in a non-blocking switch. The switch receives packets from a plurality of ingress ports, stores the packets in the common memory, and forwards the packets to a plurality of egress ports. The common memory is physically divided into two banks to provide two way interleaving. Two way interleaving is performed by reading a packet to be forwarded to an egress port from one bank concurrently with writing a packet received from an ingress port to the other bank. The common memory is physically divided into four banks to provide four way interleaving. Four way interleaving is performed by concurrently reading and writing two even banks or two odd banks. Bank balancing techniques are also provided to keep the banks of the common memory at the same level of occupancy.

On procède à l'entrelacement d'une mémoire commune, en vue d'en augmenter la largeur de bande dans un commutateur non bloquant. Le commutateur reçoit des paquets en provenance de plusieurs ports d'entrée, stocke ces paquets dans la mémoire commune et les achemine vers plusieurs ports de sortie. La mémoire commune est divisée physiquement en deux rangées, pour permettre un entrelacement à deux voies. On effectue l'entrelacement à deux voies en lisant un paquet à acheminer vers un port de sortie à partir d'une rangée, tout en inscrivant un paquet reçu en provenance d'un port d'entrée dans l'autre rangée. La mémoire commune est divisée physiquement en quatre rangées pour permettre un entrelacement à quatre voies. On effectue l'entrelacement à quatre voies par lecture et écriture simultanée de deux rangées paires ou de deux rangées impaires. On prévoit également des techniques d'équilibrage des rangées pour maintenir les rangées de la mémoire commune au même niveau d'occupation.

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