Maximum likelihood sequence estimation apparatus

Details Maximum likelihood sequence estimation apparatus Maximum likelihood sequence estimation apparatus

H - Electricity

04

L

340/71

H04L 1/00 (2006.01) H03M 13/41 (2006.01) H04L 25/03 (2006.01)

Patent

CA 2032867

A maximum likelihood sequence estimation apparatus for estimating a transmitted signal sequence from a received signal sequence and an estimated channel impulse response characteristic. A merge detection circuit computes a time required for respective merges, that is, the time required for convergence of all possible path to one state, instructs the maximum likelihood sequence estimation circuit to output a decided maximum likelihood data sequence to a channel impulse response characteristic estimation circuit based on such merge time and instructs a received signal hold circuit to output a held received signal to the channel impulse response characteristic estimation circuit. Thereafter, the channel impulse response characteristic estimation circuit immediately estimates the channel impulse response characteristic using the data from the maximum likelihood sequence estimation circuit and the received signal hold circuit. The apparatus allows the channel impulse response characteristic to be estimated at a higher speed, thus improving system efficiency.

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