Method and circuit arrangement to reduce a dc-offset

Details Method and circuit arrangement to reduce a dc-offset Method and circuit arrangement to reduce a dc-offset

H - Electricity

04

L

H04L 25/06 (2006.01) H04B 1/18 (2006.01)

Patent

CA 2241303

To reduce the DC-offset in bursts (B1, B2) of a digital signal (S1), some samples of one of the digital bursts (B1) which have no predetermined value are averaged by an averager (AV) resulting in a correction value (CV). Meanwhile the samples of this digital burst (B1) are temporarily stored in a memory (MEM1). The DC-offset correction value (CV) calculated by the averager (AV) is then subtracted from the samples of the digital bursts (B1, B2). In this way, he dynamic range of the samples is reduced significantly.

Afin de réduire le décalage de la composante continue dans les rafales (B1, B2) d'un signal numérique (S1), quelques échantillons de l'une des rafales numériques (B1) qui n'a pas de valeur prédéterminée sont moyennés par un moyenneur (AV), ce qui donne une valeur de correction (CV). Ces échantillons de la rafale (B1) sont stockés temporairement dans une mémoire (MEM1). La valeur de correction (CV) du décalage de la composante continue, calculée par le moyenneur (AV), est ensuite soustraite des échantillons des rafales numériques (B1, B2). Ainsi, la dynamique des échantillons est sensiblement réduite.

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