Dual bus microcomputer system with programmable control of...

Details Dual bus microcomputer system with programmable control of... Dual bus microcomputer system with programmable control of...

G - Physics

06

F

354/236

G06F 12/00 (2006.01) G06F 12/08 (2006.01) G06F 13/16 (2006.01)

Patent

CA 2016400

A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

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