Memory device having a crested tunnel barrier

Details Memory device having a crested tunnel barrier Memory device having a crested tunnel barrier

H - Electricity

01

L

H01L 29/788 (2006.01) H01L 29/423 (2006.01) H01L 29/51 (2006.01) H01L 29/792 (2006.01)

Patent

CA 2305230

A nonvolatile, high-speed, bit-addressable memory device is disclosed. A tunnel barrier layer is disposed between a charge supply medium and a charge storage medium, with the tunnel barrier layer having a crested energy profile with a maximum half-way between the charge storage layer and the charge supply layer.

On décrit une mémoire permanente rapide adressable au niveau du bit. Une couche limite en tunnel est disposée entre un moyen d'alimentation de charge et un élément de mémoire capacitive. Cette couche limite présente un profil d'énergie de crête dont le pic est à mi-distance entre la couche mémoire capacitive et la couche d'alimentation de charge.

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