Programmable option selection and paged memory cache...

Details Programmable option selection and paged memory cache... Programmable option selection and paged memory cache...

G - Physics

06

F

354/241

G06F 9/00 (2006.01) G06F 11/34 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2005698

PROGRAMMABLE OPTION SELECTION AND PAGED MEMORY CACHE COHERENCY CONTROL Abstract of the Disclosure A computer system which flushes the cache controller when a circuit board is being configured or is responding to an input/output write operation is described. The flush operation can be disabled for each circuit board location. A cache flush operation can also be directly requested.

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