Tri-stated driver for bandwidth-limited load

Details Tri-stated driver for bandwidth-limited load Tri-stated driver for bandwidth-limited load

H - Electricity

03

K

H03K 19/0944 (2006.01)

Patent

CA 2654553

A CMOS driver circuit is configured to provide a tri-state condition after a predetermined number of like-valued data bits have been transmitted, reducing the presence of intersymbol interference (ISI) along a transmission channel. In situations where the transmission channel is bandwidth- limited, the use of the tri-stating technique allows for the complete transition to the supply rails during the given bit period.

L'invention concerne un circuit pilote CMOS configuré de manière à passer dans l'état haute impédance lorsqu'un nombre prédéterminé de bits de données identiques ont été transmis, réduisant la présence de brouillage intersymbole (ISI) sur un canal de transmission. Dans les cas où le canal de transmission est limité en bande passante, l'utilisation de la technique trois états permet une transition complète vers les circuits d'alimentation pendant la période fixée pour les bits.

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