Fault tolerant system and controller, access control method,...

Details Fault tolerant system and controller, access control method,... Fault tolerant system and controller, access control method,...

G - Physics

06

F

G06F 11/07 (2006.01) G06F 11/16 (2006.01) G06F 13/00 (2006.01)

Patent

CA 2530921

The present invention has been made to realize access processing performed in accordance with synchronous/asynchronous state between processors in a fault tolerant system. In two systems that constitute a fault tolerant system, a router assigns, to an access packet transmitted from a CPU to an IO device, tag information including ID codes of access source and destination and information indicating whether the access packet is synchronous access. An access comparison section has buffers and that retain the packets from the CPU on a system basis, a tag check section that determines whether each packet is synchronous packet access based on the tag information assigned to the packets retained in the buffers, and a comparison section that outputs the packet from one system to an IO IF and discards the packet from other system in the case where the packet is synchronous access.

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