Graphical editor for defining memory test sequences

Details Graphical editor for defining memory test sequences Graphical editor for defining memory test sequences

G - Physics

06

F

G06F 11/28 (2006.01) G01R 31/28 (2006.01)

Patent

CA 2222665

A technique for specifying test signals such as to be applied to a memory integrated circuit, by graphically displaying and editing a sequence of test cycles, together with a graphic indication of parameters that specify which of the test cycles are to be repeated. The preparation of detailed instructions for tester equipment may therefore be carried out automatically by computer software that interprets the graphic indications and generates tester microcode. As a result, knowledge of test equipment programming is not required to prepare test programs.

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