Cpu bus allocation control

Details Cpu bus allocation control Cpu bus allocation control

G - Physics

06

F

G06F 13/366 (2006.01) G06F 13/30 (2006.01) G06F 13/362 (2006.01)

Patent

CA 2071306

An arbiter with first and second CPU timers is provided which advantageously allows measuring and controlling CPU bus ownership intervals via the arbiter. The first CPU timer, a running timer, specifies the total interval that the CPU is allocated the bus. The second timer, an idle timer, specifies an interval which the CPU may own the bus without performing an operation. The arbiter uses these two timers to dynamically adjust and control CPU bus ownership.

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