High performance passivation for semiconductor devices

Details High performance passivation for semiconductor devices High performance passivation for semiconductor devices

H - Electricity

01

L

H01L 21/469 (2006.01) H01L 21/312 (2006.01) H01L 23/29 (2006.01) H01L 23/31 (2006.01) H01L 23/532 (2006.01)

Patent

CA 2056456

A method of passivating a semiconductor device, comprises depositing a first dielectric passivation layer on the surface of the device, forming at least one planarization layer over the first passivation layer from an inorganic spin-on glass solution containing phosphorus and silicon organometallic molecules that are pre-reacted to form at least one Si~O~P bond between the phosphorus and silicon organometallic molecules, and subsequently depositing a second dielectric passivation layer on said at least one planarization layer(s). This results in improved step coverage of the underlying topography and permits much better protection against moisture related degradation than standard vapour phase deposited passivation layers even when the thickness of such layers is increased.

Affiliated with

Also associated with

Rating

High performance passivation for semiconductor devices does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with High performance passivation for semiconductor devices, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and High performance passivation for semiconductor devices will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-2049773