G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 9/302 (2006.01) G06F 7/50 (2006.01)
Patent
CA 2078319
A method and processor for evaluating numbers processes components of a pair of input numbers A, B in a plurality of identical gate structures. Each gate structure receives information from two bit positions and operates without carry information or any earlier computations to produce a conditional sum word. A control signal derived from the conditional sum word provides the same evaluation as the actual sum in fewer processing steps. A preferred embodiment produces the sticky hit for a rounding off unit in a floating point processor.
Riches Mckenzie & Herbert Llp
Sun Microsystems Inc.
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