Integrated drivers for flat panel displays employing...

Details Integrated drivers for flat panel displays employing... Integrated drivers for flat panel displays employing...

H - Electricity

03

K

H03K 19/02 (2006.01) G09G 3/20 (2006.01) H03K 19/08 (2006.01) H03K 19/195 (2006.01) H03M 1/76 (2006.01) H03M 5/20 (2006.01)

Patent

CA 2236119

The present invention defines a family of logic circuitry comprising at least one logic gate. Each logic gate comprises a plurality of chalcogenide threshold switches (OTS1, OTS2, OTS3). The logic gates of the present invention use a chalcogenide threshold switch (OTS3) as a means of discharging load capacitance and resetting logic gate output. The present invention also defines a display driver for driving a flat panel display having row and column driving lines. The display driver comprises logic gates where each logic gate is comprised of chalcogenide threshold switches (OTSI, OTS2, OTS3).

L'invention concerne une famille de circuits logiques comprenant au moins une porte logique. Chaque porte logique comprend une pluralité de commutateurs de seuil en chalcogénure (OTS1, OTS2, OTS3). Ces portes logiques utilisent un commutateur de seuil en chalcogénure (OTS3) en tant que moyen de décharge de la capacité de charge et de remise à zéro de la sortie de porte logique. L'invention concerne également un circuit d'attaque d'affichage servant à commander un panneau plan d'affichage possédant des lignes d'attaque de rangée et de colonne. Ce circuit d'attaque d'affichage comprend des portes logiques composées chacune de commutateurs de seuil en chalcogénure (OTS1, OTS2, OTS3).

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