Digital line synchronizer

Details Digital line synchronizer Digital line synchronizer

H - Electricity

04

L

363/13

H04L 7/00 (2006.01) H04J 3/06 (2006.01) H04Q 11/04 (2006.01)

Patent

CA 1046645

TITLE DIGITAL LINE SYNCHRONIZER ABSTRACT OF THE DISCLOSURE A digital line synchronizer system for use with a digital PCM TDM switching exchange will provide a vector address, off-set between the address locations of WRITE and READ vectors within a multiple frame input buffer memory bank of the incoming line equipment upon the occurrence of either a loss of receive framing synchronization or the equalization of time reference between the WRITE and READ vectors with respect to the input buffer memory bank. The vector address offset is provided to prevent the condition of information distortion due to the phenomenon of vector slippage whereby a given channel/word slot within the multiple frame memory bank is twice written with incoming PCM data under the operation of the WRITE vector address before the first stored sample of PCM data can be retreived via the use of the READ vector address.

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