Self-aligned mesfet having reduced series resistance

Details Self-aligned mesfet having reduced series resistance Self-aligned mesfet having reduced series resistance

H - Electricity

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H01L 21/8234 (2006.01) H01L 21/033 (2006.01) H01L 21/338 (2006.01) H01L 27/095 (2006.01) H01L 29/812 (2006.01)

Patent

CA 1131367

SELF-ALIGNED MESFET HAVING REDUCED SERIES RESISTANCE ABSTRACT OF THE DISCLOSURE Disclosed herein is a structure and process for a self-aligned metal semiconductor field effect transistor having the characteristics of a high speed, high density, low power LSI circuit and specifically an improved high device gain MESFET device using conventional photographic techniques. The inventive MESFET device has improved high device gain as a result of the elimination of series resistance, increased circuit in- tegration density, and improved speed capability due to the elimination of spacings between gate and drain and gate and source and the improved high device gain.

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