G - Physics – 06 – F
Patent
G - Physics
06
F
354/235
G06F 1/00 (2006.01) G06F 13/40 (2006.01)
Patent
CA 1148266
DATA INTERFACE MECHANISM FOR INTERFACING BIT -PARALLEL DATA BUSES OF DIFFERENT BIT WIDTH Abstract A data interface mechanism for interfacing bit-parallel data buses of different bit widths. This mechanism provides an automatic and efficient mechanism for converting data bytes into plural-byte data words and vice versa. The mechanism utilizes a plurality of random access (RAM) storage units located between the two data buses and an addressing structure wherein the higher order address bits are supplied to a chip select decoder to produce different chip select signals which are used to select different ones of the RAM units. For successive data transfers to or from the narrower data bus, storage addresses are used which produce different chip select signals which select the different RAM units one after the other in a sequence which repeats itself. Thus, successive data bytes to (from) the narrower bus are transferred from (to) the different RAM units in a rotating manner. For data transfers to or from the wider data bus, a storage address is used which produces a distinctive chip select signal which is different from those used for the individual narrower transfers. This distinctive chip select signal causes the storage control logic to simultaneously select all of the RAM units. This enables a simultaneous parallel transfer of data from all of the RAM units to the wider data bus or vice versa.
352390
International Business Machines Corporation
Rosen Arnold
LandOfFree
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