Chip topography for integrated circuit communication controller

Details Chip topography for integrated circuit communication controller Chip topography for integrated circuit communication controller

G - Physics

06

F

352/42, 352/82.3

G06F 13/00 (2006.01) G06F 13/12 (2006.01) G06F 13/42 (2006.01) H01L 27/02 (2006.01)

Patent

CA 1157952

CHIP TOPOGRAPHY FOR INTEGRATED CIRCUIT COMMUNICATION CONTROLLER Abstract of the Disclosure An integrated circuit for operatively connec- ting a plurality of peripheral devices to a processor includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes two independent full duplex, master peripheral ports in which each port provides two char- acter buffering on both input and output channels. Data may be transmitted using two message formats at two different clock frequencies with each channel having simultaneous sending and receiving capabilities. Data processing circuits are located adjacent the first edge which connects to the processor while the port control circuitry is located adjacent the third edge of the chip which connects to the peripheral devices.

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