System page table apparatus

Details System page table apparatus System page table apparatus

G - Physics

06

F

354/239

G06F 13/00 (2006.01) G06F 12/10 (2006.01)

Patent

CA 1155965

ABSTRACT OF THE DISCLOSURE In this apparatus for dynamically translating virtual memory addresses to real memory addresses) a master system page table maintained in a memory associates real memory addresses with their corresponding system virtual memory addresses. This table is organized with each virtual memory address stored in it at an index location which is a smaller value formed as a predetermined function of the virtual memory address value. The translator forms the index from the virtual memory address according to the function, enters the table with it, and extracts the corresponding real memory address. In a preferred embodiment, every process (i.e., job) may reference any address in any segment of a process virtual address space, and a dedicated mechanism converts such a process virtual address reference to a system virtual memory address, which then is converted to the real memory address.

373270

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