Vertical synchronization circuit for television receivers

Details Vertical synchronization circuit for television receivers Vertical synchronization circuit for television receivers

H - Electricity

04

N

350/89

H04N 5/06 (2006.01) H04N 5/12 (2006.01)

Patent

CA 1133118

ABSTRACT An improved vertical synchronization system for a television receiver provides both good noise immunity and improved interlace. This is acheived by employing two parallel vertical synchronization circuits between the synchronizing signal input of the vertical oscillator and the synchronizing signal source. One of these vertical synchronizing circuit paths comprises a standard integrator circuit adjusted for optimum noise immunity and the other is a cascaded digital circuit adjusted for improved interlace but having poorer noise immunity than the first circuit. The digital circuit produces a synchronizing pulse slightly ahead of the pulse produced by the conventional circuit so that the digital circuit normally controls the operation of the oscillator. Whenever extreme noise conditions exist, the digital circuit is disabled and the conventional synchronizing signal circuit takes o?er the synchronizing task.

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