Multibus processor for increasing execution speed using a...

G - Physics – 06 – F

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354/232

G06F 9/30 (2006.01) G06F 9/38 (2006.01)

Patent

CA 1119731

ABSTRACT OF THE INVENTION A computing apparatus having at least three data buses and a plurality of elementary function modules is disclosed. Each module is connected to at least one of the buses and at least one of the modules is connected to at least three of the buses. The buses each comprise a plurality of individual lines organized into groups: a group of source address lines, a group of destination address lines, and a group of data carrying lines. A control means is connected to each of the buses for directing the opera- tion of the apparatus and the control means places source and destination addresses on the bus source address and destination address lines respectively for effectively connecting or configur- ing the function modules according to a selected program controlled configuration. The apparatus is useful in carrying out a plural- ity of machine operations during a single machine instruction cycle.

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