Instruction prefetch for high speed compact digital computer...

Details Instruction prefetch for high speed compact digital computer... Instruction prefetch for high speed compact digital computer...

G - Physics

06

F

354/230.71

G06F 9/22 (2006.01)

Patent

CA 1142651

ABSTRACT Therein is disclosed high speed, compact computer system architecture. System architecture includes a processor for processing machine language data, a memory for storing at least machine language instructions for use by processor, microinstruc- tion logic for storing and providing sequences of frequently used instructions, and busses for trasmitting at least instructions between processor and memory. Microinstruction memory circuitry is disclosed for efficient storage of microinstructions in available microinstruction memory space. Also disclosed is microinstruction selection circuitry for high speed selection of successive micro- instructions of a sequence. Instruction prefetch circuitry is disclosed for fetching from memory a next instruction to be executed while a current instruction is being executed. Time required to execute successive instructions is thereby reduced and circuitry required to perform instruction prefetch is simplified. jr/

393674

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