Digital phase lock loop circuit

Details Digital phase lock loop circuit Digital phase lock loop circuit

H - Electricity

03

B

328/163, 331/34

H03B 5/00 (2006.01) H03B 19/00 (2006.01) H03B 21/00 (2006.01) H03L 7/00 (2006.01) H03L 7/16 (2006.01)

Patent

CA 1083235

DIGITAL PHASE LOCK LOOP CIRCUIT ABSTRACT OF THE DISCLOSURE Herein disclosed is a digital phase lock loop circuit wherein the phase and the frequency of an output clock pulse of the circuit are made to instantaneously coincide with the phase and the frequency of an input clock pulse of the circuit. The digital phase lock loop circuit includes a fixed frequency generator circuit, an output frequency divider to which a standard clock pulse from the fixed frequency generator circuit is supplied via an inhibit gate, an output clock pulse frequency divider which divides the frequency of the output clock pulse from the output frequency divider, a phase comparator to which the input clock pulse, the divided clock pulse from the output clock pulse frequency divider and an inhibit pulse generator to which the output of the phase comparator are supplied, for supplying the inhibit pulse from the inhibit pulse generator to the inhibit gate. According to the present invention, a clear pulse generator is provided for the purpose of forming a clear pulse which clears the contents of the output frequency divider and the output clock frequency divider. Such clear pulse is generated during a condition when the time difference between a first occurrence at which the frequency division of the output frequency divider is actuated by the standard clock pulse after the output frequency divider and the output clock frequency divider are cleared by the clear pulse, and a second occurrence at which the frequency division of the input frequency divider is actuated by the input clock pulse, is smaller than a predetermined period of the standard clock pulse. - 1 -

290326

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