Plural virtual address space processing system

Details Plural virtual address space processing system Plural virtual address space processing system

G - Physics

06

F

354/241

G06F 12/10 (2006.01)

Patent

CA 1074455

ABSTRACT OF THE DISCLOSURE In a data processing system having a plurality of virtual address spaces, a virtual address is translated into a real address for accessing a main memory and the translation result is stored in a translation look aside buffer, as in a processing system having a single virtual address space. Thereafter, in the case of the same virtual address as the above, the trans- lation look aside buffer is retrieved to translate the virtual address into a real address. Generally, even in the case of the same virtual addresses, if their virtual address spaces are different, the virtual addresses are translated into different real addresses. However, a control program, a control table or a common subroutine is provided in a common area in which the coordination of virtual and real addresses is always constant even in the case of different virtual address spaces. To enhance the efficiency of utilization of the translation look aside buffer, common area indicating means is provided, by which the coordination of virtual and real addresses on the translation look aside buffer is registered so that it can be used in common to a plurality of virtual address spaces.

279994

Affiliated with

Also associated with

Rating

Plural virtual address space processing system does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Plural virtual address space processing system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Plural virtual address space processing system will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-565700