Charge transfer logic gate

Details Charge transfer logic gate Charge transfer logic gate

H - Electricity

01

L

328/127

H01L 27/10 (2006.01) H01L 29/423 (2006.01) H01L 29/768 (2006.01) H01L 29/78 (2006.01) H03K 19/08 (2006.01) H03K 21/00 (2006.01)

Patent

CA 1049142

CHARGE TRANSFER LOGIC GATE Abstract of the Disclosure A charge transfer logic gate comprises a plurality n of one-bit shift registers which fan-in to the series combination of a logic cell and an output cell. Each shift register comprises the series combination of two subcells, each of area A. The subcells are separated from one another, and from the logic cell, by potential barriers of magnitude VB established illustratively by ion implantation. The areas of the logic and output cells are both n x A and the two are separated by a threshold potential barrier of magnitude VT. To detect the presence of m and n inputs applied to separate ones of the shift registers (2< m <n), the thresh- old barrier is preferably made to be Image . The subcells of each shift register, as well as the logic and output cells, are connected to suitable phases of a clock in order to perform a variety of logic functions such as AND and OR. When the inputs constitute continuous data streams, a dump gate is coupled to the logic cell to remove charge remaining therein after each logic operation is per- formed.

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