Chip package with high capacitance, stacked vlsi/power...

Details Chip package with high capacitance, stacked vlsi/power... Chip package with high capacitance, stacked vlsi/power...

H - Electricity

05

K

356/9

H05K 7/08 (2006.01) H01L 23/64 (2006.01) H05K 1/14 (2006.01) H05K 7/06 (2006.01) H05K 7/12 (2006.01)

Patent

CA 1137646

CHIP PACKAGE WITH HIGH CAPACITANCE, STACKED VLSI/POWER SHEETS EXTENDING THROUGH SLOTS IN SUBSTRATE ABSTRACT A packaging module for VLSI chips of very high densities and very small size is constructed of a substrate through which a number of slots have been milled. Into each slot a stack of several capacitively coupled, insulated power sheets for connecting power to chips from bus lines and a shielded ribbon conductor are inserted. Preferably, the power sheets are oriented perpendicularly to the substrate. The upper edges of the power sheets are arranged flush with the top surface of the substrate so that the edges themselves form land areas upon which a chip connector can be fastened. Alternatively, an interconnection layer can be disposed between the top edges of the sheets as well as to the surface of the substrate and the chip connectors. The lower portions of the power sheets extend below the substrate to provide power connection tabs and decoupling capacitor connection tabs. YO978-066

349745

Affiliated with

Also associated with

Rating

Chip package with high capacitance, stacked vlsi/power... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Chip package with high capacitance, stacked vlsi/power..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Chip package with high capacitance, stacked vlsi/power... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-617435