H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/166
H01L 21/78 (2006.01) H01L 21/00 (2006.01) H01L 21/033 (2006.01) H01L 21/28 (2006.01) H01L 21/3213 (2006.01) H01L 21/3215 (2006.01) H01L 21/8244 (2006.01) H01L 23/535 (2006.01) H01L 27/06 (2006.01)
Patent
CA 1040749
ABSTRACT: A method of defining, a fine line low resis- tivity pattern in a layer of high resistivity poly- crystalline semiconductor material present on an insulating layer on the surface of a semiconductor body by lateral impurity diffusion under the edge of a masking layer present on the polycrystalline semiconductor material. The undiffused polycrystalline semiconductor material mayor may not subsequently be removed depending upon the application of the method. In one form the fine line pattern is selectively re- moved to leave a precisely defined aperture of narrow width in the polycrystalline layer. In one specific embodiment described the method is employed to define high impedance load transistors in a silicon gate integrated circuit. In another specific embodiment described the method is employed to define a compact crossing connection between a polycrystalline silicon line on an oxide layer and an underlying diffused con- nection region in a silicon gate integrated circuit. Figure 1(c) is suitable for publication purposes. - 50 -
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