Method of high current ion implantation

H - Electricity – 01 – L

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H01L 21/265 (2006.01) H01L 21/3115 (2006.01) H01L 21/425 (2006.01) H01L 21/46 (2006.01) H01L 21/78 (2006.01)

Patent

CA 1043474

A METHOD OF HIGH CURRENT ION IMPLANTATION Abstract of Disclosure A method of ion implantation is provided which is particularly applicable to the fabrication of integrated circuits with high current ion implantation apparatus utilizing ion beams having currents of at least 0.5 ma. The method avoids excessive charge buildup on semiconductor wafer surfaces which may destroy the surface electrical in- sulation, thereby rendering the integrated circuit ineffec- tive. The method involves forming in a layer of elec- trically insulative material over the wafer, a plurality of openings through the insulative layer in the various chip areas to expose the semiconductor wafer surfaces which are to be ion implanted with conductivity-determining impuri- ties, and in addition, forming openings through the insula- tive layer over the kerf area between wafer chips to expose wafer kerf adjacent to the chip openings. The total area exposed in the wafer kerf must be greater than the total area exposed in said chip wafer openings. Then, a beam of ions having sufficient energy to implant ions in the ex- posed wafer in said chip area and kerf openings is directed at the wafer. The presence of the kerf openings avoids the problem of charge buildup. Then, the kerf area is removed by conventional dicing to separate the wafer into a plurality of chips.

289545

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