Method of producing polysilicon structures in the 1 um range...

Details Method of producing polysilicon structures in the 1 um range... Method of producing polysilicon structures in the 1 um range...

H - Electricity

01

L

204/96.05, 204/9

H01L 21/306 (2006.01) C04B 41/53 (2006.01) H01L 21/3213 (2006.01)

Patent

CA 1165724

ABSTRACT OF THE DISCLOSURE Polysilicon structures down to a 1 µm range on substrates containing integrated semiconductor circuits are produced by plasma etching in a plate reactor with the use of SF6 and an inert gas as the reactive gas. During this process, a semiconductor crystal wafers covered with a SiO2 layer and a polysilicon layer is provided with an etch mask and positioned on a grounded electrode of the plate reactor and an etching process, which achieves a high selectivity of polysilicon to SiO2 and to the etch mask, is carried out with a HF power, P, of < 0.1 watt/cm2, a gas pressure, p, ranging from 60 to 120 Pa, and an electrode temperature ranging from 20° to 60°C. With the inventive process, large scale integrated semiconductor circuits are produced in a single stage sequence with high etching selectivity, uniform etching and a high throughput of silicon wafers.

395211

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