Semiconductor memory element operable at high speed and with...

H - Electricity – 03 – K

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H03K 17/00 (2006.01) G11C 11/40 (2006.01) G11C 11/411 (2006.01) H03K 3/286 (2006.01) H03K 3/352 (2006.01)

Patent

CA 1052908

MEMORY CIRCUIT ABSTRACT OF THE DISCLOSURE A memory circuit comprises a semiconductor element circuit having equivalently a PNPN four-layer structure, at least an NPN transistor and a diode. An N-type emitter of the semiconductor element cir- cuit is connected to the base of the NPN transistor, while a P-type base of the circuit is connected to the collector of the NPN transistor through the diode. The semiconductor element circuit has a positive feedback loop which is additionally provided with another feedback loop extending across the P-type base and the N-type emitter of the semiconductor element circuit, whereby in the ON holding state of the memory circuit the semiconductor element circuit is operated as a current stabilizing circuit and the transistor included in the additional feedback loop is stabilized in a controlled staturation state. The memory circuit can thus be operated at a high speed with a low power consumption.

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