High density wafer contacting and test system

Details High density wafer contacting and test system High density wafer contacting and test system

G - Physics

01

R

356/117

G01R 31/26 (2006.01) G01R 1/073 (2006.01) G01R 31/02 (2006.01) G01R 31/28 (2006.01)

Patent

CA 1041225

HIGH DENSITY WAFER CONTACTING AND TEST SYSTEM ABSTRACT The instant invention is more particularly directed to a contractor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a plurality of discrete electrical probes geometrically arranged, or oriented, to respectively electrically contact a discrete one of said array of con- ductive pads on said packaging substrate or said semiconductor device. The contactor structure further includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits. Each of said first integrated circuits contains cir- cuitry, whereby said selected first and second ones of said first circuits will manifest the electrical integrity of the electrical path there between. Namely, the electrical path whose integrity is manifested is the conductive path in the device or substrate under test. - 1 -

239720

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