G - Physics – 06 – F
Patent
G - Physics
06
F
340/81
G06F 15/16 (2006.01) G06F 5/10 (2006.01) G06F 15/167 (2006.01)
Patent
CA 1099363
ABSTRACT OF THE DISCLOSURE Two computers are controlled each by timing periods produced by its own clock and work therefore asynchronously. Each computer is provided with a pulse treatment circuit which breaks, owing to a break signal, the computer work during the following timing period. A buffer memory is used in order to transfer information from the first to the second of the computers. The asynchronism causes a risk that the buffer memory becomes totally occupied and unoccupied, respective- ly. The risk is eliminated by means of an address and break signal generator which generates addresses to control writing and reading of the buffer-memory and generates break signals which are sent to the pulse treatment circuit of the first and second computer in order to inhibit that information is sent to and received from the buffer memory, respectively. The writing and reading addresses are generated by means of a first and a second circulating address counter stepped by the pulse treatment circuit of the first and second computer, respectively. The break signals are generated by means of a comparator connected to the two address counters. The timing periods have parts during which the computer components work unreliably due to their reaction times. A reliability device compares therefore the phases of the timing periods produced by the two computer clocks in order to allow only break singals which are generated owing to the comparison of addresses obtained in period parts during which both address counters are reliable.
297015
Marks & Clerk
Telefonaktiebolaget Lm Ericsson
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