Self-registering method of fabricating field effect transistors

Details Self-registering method of fabricating field effect transistors Self-registering method of fabricating field effect transistors

H - Electricity

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H01L 27/10 (2006.01) H01L 21/314 (2006.01) H01L 21/316 (2006.01) H01L 21/318 (2006.01) H01L 21/768 (2006.01) H01L 29/76 (2006.01)

Patent

CA 1078077

SELF-REGISTERING METHOD OF FABRICATING FIELD EFFECT TRANSISTORS Abstract of the Disclosure A method of fabricating a field effect transistor (FET) wherein a self-registered or misregistration tolerant electrical connection is provided between the gate electrode and a metallic interconnection line. The method involves a unique structure which includes a thick deposited oxide insulation layer and an etch stopping layer over doped silicon source and drain regions, over polysilicon gate electrode regions, and over field isolation regions. The etch stopping layer facilitates fabrication of a self- registering electrical connection between the gate electrode and a metallic interconnection line wherever desired. The thick deposited oxide layer pro- vides reduced capacitive coupling between the insulated regions and the metallic interconnection line when compared to known self-registered gate contacting methods that employ only thermally grown oxide insulation. The method also includes the provision for controlling the removal of insulation over the gate electrode wherever desired without seriously degrading the insulation over other parts of the structure. The disclosed method further relates to fabricating an integrated circuit containing FETs having a self-registered electrical connection between the gate electrode and the metallic interconnection line, the gate electrode self-aligned with respect to the source and drain regions, and wherein FETs of the integrated circuit have: a channel region; a gate insulator; an electrically conductive gate electrode; source and drain regions; thick insulation over the source and drain and over the gate electrode except in the contact areas; field isolation or field shield regions between FETs of the integrated circuit; metallic-type high electrical conductivity interconnection line; and self-registering electrical connection between the gate and the interconnection line. -1-

279093

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