High speed-low cost, clock controlled cmos logic implementation

Details High speed-low cost, clock controlled cmos logic implementation High speed-low cost, clock controlled cmos logic implementation

H - Electricity

03

K

354/231, 328/87

H03K 17/00 (2006.01) H03K 19/017 (2006.01) H03K 19/08 (2006.01) H03K 19/096 (2006.01)

Patent

CA 1042519

HIGH SPEED-LOW COST, CLOCK CONTROLLED CMOS LOGIC IMPLEMENTATION ABSTRACT OF THE DISCLOSURE A uniquely arranged, clock-controlled integrated circuit is disclosed as a building block for implementing Boolean logic functions. The circuit provides a source for supplying a plurality of reference potentials, and a data node adapted to be selectively charged to a first of the reference potentials and discharged to a second of these potentials. A current source connected to the data node is adapted to selectively charge the data node to a first of the reference potentials, this current source including a source of constant current and a source of periodic current. The source of constant current is connected to the reference potential source to charge the data node to the first reference potential. The source of periodic current receives a clocking signal so as to periodically charge the data node to the first reference potential. The circuit includes a conduction path connected between the data node and the reference potential source for selectively discharging the data node through the conduction path to the second of the reference potentials. The circuit has a minimum number of components and a design to yield a low cost, high speed operation. The circuit may also include an efficient signal inversion and amplification s stage, where such is required.

235949

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