Differential pulse coded system using shift register companding

Details Differential pulse coded system using shift register companding Differential pulse coded system using shift register companding

H - Electricity

04

B

354/69

H04B 14/06 (2006.01) H03M 3/04 (2006.01)

Patent

CA 1053373

DIFFERENTIAL PULSE CODED SYSTEM USING SHIFT REGISTER COMPANDING Abstract of the Disclosure A digital accumulator employing a reversible shift register converts a 1-bit differential pulse code to a logarithmically companded, or n:m, pulse code. The accumulator is coupled through a digital-to-analog converter to a subtraction circuit which also receives an analog signal to be represented in the differential pulse code. Output from the subtractor is integrated and thresholded to produce the differential pulse code. A decoder using the same type of accumulator is also shown.

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